Datacom Systems D56 Spécifications Page 38

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Vue de la page 37
Si5040
38 Rev. 1.3
Figure 23. Device Interrupt Tree
RX_REFLOS
Interrupt Status (sticky) bit
(Register 5, bit 6)
RX_REFLOS
Interrupt mask bit
(Register 4, bit 6)
RX_LOS
Interrupt Status (sticky) bit
(Register 5, bit 5)
RX_LOS
Interrupt mask bit
(Register 4, bit 5)
RX_LOL
Interrupt Status (sticky) bit
(Register 5, bit 4)
RX_LOL
Interrupt mask bit
(Register 4, bit 4)
TX_REFLOS
Interrupt Status (sticky) bit
(Register 133, bit 6)
TX_REFLOS
Interrupt mask bit
(Register 132, bit 6)
TX_LOS
Interrupt Status (sticky) bit
(Register 133, bit 5)
TX_LOS
Interrupt mask bit
(Register 132, bit 5)
TX_LOL
Interrupt Status (sticky) bit
(Register 132, bit 4)
TX_LOL
Interrupt mask bit
(Register 132, bit 4)
INTERRUPT
Interrupt pin
(Open drain or LVTTL , Active Low)
Write-to-Clear
10 MHz Clock
TX_LOL
Alarm status bit
(Register 137, bit 4)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
10 MHz Clock
TX_LOS
Alarm status bit
(Register 137, bit 5)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
10 MHz Clock
TX_REFLOS
Alarm status bit
(Register 137, bit 6)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
10 MHz Clock
RX_LOL
Alarm status bit
(Register 9, bit 4)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
10 MHz Clock
RX_LOS
Alarm status bit
(Register 9, bit 5)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
10 MHz Clock
RX_REFLOS
Alarm status bit
(Register 9, bit 6)
CK
D
Q
C
Interrupt Enable
(Register 2, bit 5)
Clear
Vue de la page 37
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