Datacom Systems D56 Spécifications télécharger pdf (Page 37)

Si5040

Rev. 1.3 37

11. Interrupt Functionality

Alarm Status bits (Register 9/137) are sampled by a 10 MHz clock to create the Interrupt Status bits (Register

5/133). If the Interrupt Enable bit (Register 2, bit 5) is a zero, all the Interrupt status bits are forced to zero. The

Alarm Status bits are always active regardless of the state of the Interrupt Enable bit and the Interrupt Mask bits.

The Interrupt Mask bits (Register 4/132) masks the Alarms Status bits from affecting the corresponding Interrupt

Status bit. Writing a zero to an Interrupt Status bit forces that bit to a zero; however, if the corresponding Alarm bit

is active and the Interrupt Mask bit is not set, the next 10 MHz clock cycle will again cause the Interrupt Status bit to

set. All of the Interrupt Status bits are logically “NORed” together to create the Interrupt bit (or pin16). Please refer

to Figure 23 for an illustration of the device interrupt tree. The polarity of the Interrupt (pin 16) is active low.

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 107 108

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Datacom Systems D56 Spécifications Page 37